UNIT-II

2.1 NUMBER REPRESENTATION:

2.1.1. Positional Number Representation:

Unsigned Integers:

The simplest numbers to consider are the integers. We will begin by considering positive integers and then expand the discussion to include negative integers. Numbers that are positive only are called unsigned, and numbers that can also be negative are called signed.

            An n-bit unsigned binary number B = bn−1  bn−2 · · · b1b0

            Represents an integer that has the value

V (B) =

                                             = 

Octal and Hexadecimal Representations:

1. The positional number representation can be used for any radix. If the radix is r, then the number

K = k _n−1 k _n−2 · · · k ₁ k ₀

            Has the value

V(K)  =

2. Our interest is limited to those radices that are most practical. We will use decimal numbers because they are used by people, and we will use binary numbers because they are used by computers.

3. In addition, two other radices are useful—8 and 16. Numbers represented with radix 8 are called octal numbers, while radix-16 numbers are called hexadecimal numbers.

4. In octal representation the digit values range from 0 to 7. In hexadecimal representation (often abbreviated as hex), each digit can have one of 16 values. The first ten are denoted the same as in the decimal system, namely, 0 to 9. Digits that correspond to the decimal values 10, 11, 12, 13, 14, and 15 are denoted by the letters, A, B, C, D, E, and F.

5. In computers the dominant number system is binary. The reason for using the octal and hexadecimal systems is that they serve as a useful shorthand notation for binary numbers.

6. Below table gives the first 18 integers in these number systems.

          

 

Table. Numbers in different systems.

7. One octal digit represents three binary bits. Thus a binary number is converted into an octal number by taking groups of three bits, starting from the least-significant bit, and replacing them with the corresponding octal digit. For example, 101011010111 is converted as

                                                 101         011          010            111

                                                 5              3               2                 7                                        

8. Which means that (101011010111)₂ = (5327)₈.

9. If the number of bits is not a multiple of three, then we add 0s to the left of the most-significant bit. For example, (10111011)₂ = (273)₈ because of the grouping

10. Conversion from octal to binary is just as straightforward; each octal digit is simply replaced by three bits that denote the same value.

11. Similarly, a hexadecimal digit represents four bits. For example, a 16-bit number is represented by four hex digits, as in

(1010111100100101)₂ = (AF25)₁₆

                                                Using the grouping

12. Zeros are added to the left of the most-significant bit if the number of bits is not a multiple of four. For example, (1101101000)₂ = (368)₁₆ because of the grouping

13. Conversion from hexadecimal to binary involves straightforward substitution of each hex digit by four bits that denote the same value.

14. Binary numbers used in modern computers often have 32 or 64 bits. Written as binary n-tuples (sometimes called bit vectors), such numbers are awkward for people to deal with. It is much simpler to deal with them in the form of 8- or 16-digit hex numbers.

2.1.2. Addition of Unsigned Numbers:

1. Binary addition is performed in the same way as decimal addition except that the values of  individual digits can be only 0 or 1.

2. The one-bit addition entails four possible combinations, as indicated in Figure a. Two bits are needed to represent the result of the addition. The right-most bit is called the sum, s. The left-most bit, which is produced as a carry-out when both bits being added are equal to 1, is called the carry,

Fig. One bit addition

3. The addition operation is defined in the form of a truth table in part (b) of the figure

4. A more interesting case is when larger numbers that have multiple bits are involved. Then it is still necessary to add each pair of bits, but for each bit position i, the addition operation may include a carry-in from bit position i − 1.

5. Below figure .a presents an example of the addition operation. The two operands are X = (01111)₂ = (15)₁₀ and Y = (01010)₂ = (10)₁₀.

6. Five bits are used to represent X and Y, making it possible to represent integers in the range from 0 to 31; hence the sum S = X + Y = (25)₁₀ can also be denoted as a five-bit integer.

7. Note the labeling of individual bits, such that X = x₄ x₃ x₂ x₁ x₀ and Y = y₄ y₃ y₂ y₁ y₀. The figure shows, in a pink color, the carries generated during the addition process. For example, a carry of 0 is generated when x₀ and y₀ are added; a carry of 1 is produced when x₁ and y₁ are added, and so on.

Fig. Addition of multibit numbers

8. For bit position 0, there is no carry-in,for each other bit position i, the addition involves bits x_i and y_i , and a carry-in c_i , as illustrated in Figure b. This observation leads to the design of a logic circuit that has three inputs x_i , y_i , and c_i , and produces the two outputs s_i and c_i+1.

2.1.3. Signed Numbers:

1. In the decimal system the sign of a number is indicated by a + or − symbol to the left of the most-significant digit. In the binary system the sign of a number is denoted by the  left-most bit. For a positive number the left-most bit is equal to 0, and for a negative number it is equal to 1.

2. Therefore, in signed numbers the left-most bit represents the sign, and the remaining n − 1 bits represent the magnitude,

3. In unsigned numbers all bits represent the magnitude of a number; hence all n bits are significant in defining the magnitude. Therefore, the MSB is the left-most bit, b_n−1. In signed numbers there are n − 1 significant bits, and the MSB is in bit position b_n−2.

        

Fig. Formats for representation of integers

Negative Numbers:

Negative numbers can be represented in three different ways:

1. Sign-and-magnitude

2. 1’s complement

3.  2’s complement

1. Sign-and-Magnitude Representation:

 1. In the familiar decimal representation, the magnitude of both positive and negative   numbers is expressed in the same way. The sign symbol distinguishes a number as  being positive or negative. This scheme is called the sign-and-magnitude number representation.

2. The same scheme can be used with binary numbers in which case the sign bit is 0 or 1 for positive or negative numbers, respectively. For example, if we use four-bit numbers, then +5 = 0101 and −5 = 1101.

3.  This representation is not well suited for use in computers. More suitable representations are based on complementary systems.

1’s Complement Representation :

1. In a complementary number system, the negative numbers are defined according to a subtraction operation involving positive numbers. We will consider two schemes for binary numbers: the 1’s complement and the 2’s complement.

2. In the 1’s complement scheme, an n-bit negative number, K, is obtained by subtracting itsequivalent positive number, P, from 2ⁿ − 1; that is, K = (2ⁿ − 1) − P.

3. For example, if n = 4

            Then                 K = (2⁴ − 1) – P

                                         = (15)₁₀ − P = (1111)₂ − P

3. If we convert +5 to a negative

            We get               −5 = 1111 − 0101 = 1010

            Similarly             +3 = 0011

            And                  −3 = 1111 − 0011 = 1100

4. Clearly, the 1’s complement can be obtained simply by complementing each bit of the number, including the sign bit.

5. While 1’s complement numbers are easy to derive, they have some drawbacks when used in arithmetic operations, as we will see in the next section.

2’s Complement Representation

1. In the 2’s complement scheme, a negative number, K, is obtained by subtracting its equivalent positive number, P, from 2ⁿ; namely, K = 2ⁿ − P.

            Using our four-bit example

                                                 −5 = 10000 − 0101 = 1011

             And                              −3 = 10000 − 0011 = 1101

2. Finding 2’s complements in this manner requires performing a subtraction operation that involves borrows.

3. However, we can observe that if K₁ is the 1’s complement of P and K₂ is the 2’s complement of P, then

                                                K₁ = (2ⁿ − 1) – P

                                                K₂ = 2ⁿ – P

4. It follows that K₂ = K₁ + 1. Thus a simpler way of finding a 2’s complement of a number is to add 1 to its 1’s complement because finding a 1’s complement is trivial.

5. This is how 2’s complement numbers are obtained in logic circuits that perform arithmetic operations. There is a simple rule that can be used for this purpose.

Rule for Finding 2’s Complements

1. Given a number B = b_n−1 b_n−2 · · · b₁b₀, its 2’s complement, K = k_n−1 k_n−2 · · · k₁ k₀, can be found by examining the bits of B from right to left and taking the following action: copy all bits of B that are 0 and the first bit that is 1; then simply complement the rest of the bits.

2. For example, if B = 0110, then we copy k₀ = b₀ = 0 and k₁ = b₁ = 1, and complement the rest so that k₂ = b₂ = 0 and k₃ = b₃ = 1. Hence K = 1010.

3. As another example, if B = 10110100 then we copy k₀ = b₀ = 0,k₁ = b₁ = 0, k₂ = b₂ = 1  and  complement the rest so that k₃ = b₃ = 1  and k₄ = b₄ = 0 and k₅ = b₅ = 0 and k₆ = b₆ = 1  and k₇ = b₇ = 0, Then K = 01001100.

4. Below table illustrates the interpretation of all 16 four-bit patterns in the three signed number representations that we have considered.

Table. Interpretation of four-bit signed integers.

5. Note that for both sign-and-magnitude representation and for 1’s complement representation there are two patterns that represent the value zero.

6. For 2’s complement there is only one such pattern. Also, observe that the range of numbers that can be represented with four bits in 2’s complement form is −8 to +7, while in the other two representations it is −7 to +7.

7. Using 2’s-complement representation, an n-bit number B = b_n−1 b_n−2 · · · b₁b₀ represents the value

             V(B) = (−b_n-1 × 2^n-1) + b _n-2 × 2^n-2  +· · ·+ b₁ × 2¹  + b₀ × 2⁰  

8. Thus the largest negative number, 100 . . . 00, has the value −2 ^n-1. The largest positive number, 011 . . . 11, has the value 2 ^n-1 − 1.

2.2. ADDITION AND SUBTRACTION:

1. To assess the suitability of different number representations, it is necessary to investigate their use in arithmetic operations—particularly in addition and subtraction.

2. We can illustrate the good and bad aspects of each representation by considering very small numbers. We will use four-bit numbers, consisting of a sign bit and three significant bits.

3. Addition of positive numbers is the same for all three number representations. It is actually the same as the addition of unsigned numbers.

4. But there are significant differences when negative numbers are involved. The difficulties that arise become apparent if we consider operands with different combinations of signs.

Sign-and-Magnitude Addition

1. If both operands have the same sign, then the addition of sign-and-magnitude numbers is simple. The magnitudes are added, and the resulting sum is given the sign of the operands.

2. However, if the operands have opposite signs, the task becomes more complicated. Then it is necessary to subtract the smaller number from the larger one.

3. This means that logic circuits that compare and subtract numbers are also needed. We will see shortly that it is possible to perform subtraction without the need for this circuitry. For this reason, the sign-and-magnitude representation is not used in computers.

1’s Complement Addition

1. An obvious advantage of the 1’s complement representation is that a negative number is generated simply by complementing all bits of the corresponding positive number.

2. Below figure shows what happens when two numbers are added. There are four cases to consider in terms of different combinations of signs. As seen in the top half of the figure, the computation of 5 + 2 = 7 and (−5) + 2 = (−3) is straightforward; a simple addition of the operands gives the correct result. Such is not the case with the other two possibilities.

3. Computing 5 + (−2) = 3 produces the bit vector 10010. Because we are dealing with four-bit numbers, there is a carry-out from the sign-bit position. Also, the four bits of the result represent the number 2 rather than 3, which is a wrong result.

4. Interestingly, if we take the carry-out from the sign-bit position and add it to the result in the least-significant bit position, the new result is the correct sum of 3.

Fig. Examples of 1’s complement addition

5. A similar situation arises when adding (−5) + (−2) = (−7). After the initial addition the result is wrong because the four bits of the sum are 0111, which represents +7 rather than −7. But again, there is a carry-out from the sign-bit position, which can be used to correct the result by adding it in the LSB position

6. The conclusion from these examples is that the addition of 1’s complement numbers may or may not be simple. In some cases a correction is needed, which amounts to an extra addition that must be performed.

2’s Complement Addition

1. Consider the same combinations of numbers as used in the 1’s complement example. Below figure indicates how the addition is performed using 2’s complement numbers.

 

Fig. Examples of 2’s complement addition.

2. Adding 5 + 2 = 7 and (−5) + 2 = (−3) is straightforward. The computation 5 + (−2) = 3 generates the correct four bits of the result, namely 0011. There is a carry-out from the sign-bit position, which we can simply ignore.

 3. The fourth case is (−5) + (−2) = (−7). Again, the four bits of the result, 1001, give the correct sum (−7). In this case also, the carry-out from the sign-bit position can be ignored.

4. As illustrated by these examples, the addition of 2’s complement numbers is very simple. When the numbers are added, the result is always correct. If there is a carry-out from the sign-bit position, it is simply ignored.

5. Therefore, the addition process is the same, regardless of the signs of the operands. It can be performed by an adder circuit.

6. Hence the 2’s complement notation is highly suitable for the implementation of addition operations.

2’s Complement Subtraction

1. The easiest way of performing subtraction is to negate the subtrahend and add it to the minuend. This is done by finding the 2’s complement of the subtrahend and then performing the addition. Below figure illustrates the process.

Fig. Examples of 2’s complement subtraction.

        

2. The operation 5 − (+2) = 3 involves finding the 2’s complement of +2, which is 1110. When this number is added to 0101, the result is 0011 = (+3) and a carry-out from the sign-bit position occurs, which is ignored. A similar situation arises for (−5) − (+2) = (−7). In the remaining two cases there is no carry-out, and the result is correct.

3. Subtraction operation can be realized as the addition operation, using a 2’s complement of the subtrahend, regardless of the signs of the two operands. Therefore, it should be possible to use the same adder circuit to perform both addition and subtraction.

2.3. COMBINATIONAL CIRCUIT BUILDING BLOCKS:

Combinational Logic Design:

1. Logic circuits for digital systems may be combinational or sequential. The output of a combinational circuit depends on its present inputs only.

2. Combinational circuit processing operation fully specified logically by a set of Boolean functions .A combinational circuit consists of input variables, logic gates and output variables.

3. Both input and output data are represented by signals, i.e., they exists in two possible values. One is logic –1 and the other logic 0.

 

4. For n input variables, there are 2ⁿ possible combinations of binary input variables .For each possible input Combination, there is one and only one possible output combination.

5. A combinational circuit can be described by m Boolean functions one for each output variables.

6. Design Procedure:

   The problem is stated

         1.         The number of available input variables and required output variables is determined.

         2.         The input and output variables are assigned letter symbols.

         3.         The truth table that defines the required relationship between inputs and outputs is  derived.

         4.         The simplified Boolean function for each output is obtained.

         5.         The logic diagram is drawn.

2.3.1. Adders and Subtractors:

Adders:

Half Adder:

1. This circuit, which implements the addition of only two bits, is called a half-adder.

2. Consider the addition of 2 one-bit numbers, as an example in the context of general adder circuits.

3. The one-bit addition entails four possible combinations, as indicated in Figure a shown below .Two bits are needed to represent the result of the addition.

4. The right-most bit is called the sum, s. The left-most bit, which is produced as a carry-out when both bits being added are equal to 1, is called the carry, c. The addition operation is defined in the form of a truth table in part (b) of the figure.

Fig. Half-adder.

5. The sum bit s is the XOR function. The carry c is the AND function of inputs x and y. A circuit realization of these functions is shown in Figure c.

6. A more interesting case is when larger numbers that have multiple bits are involved. Then it is still necessary to add each pair of bits, but for each bit position i, the addition operation may include a carry-in from bit position i − 1.Figure 3.2a presents an example of the addition operation.

 

Fig. Addition of multibit numbers.

7. The two operands are X = (01111)₂ = (15)₁₀ and Y = (01010)₂ = (10)₁₀. Five bits are used to represent X and Y, making it possible to represent integers in the range from 0 to 31; hence the sum S = X + Y = (25)₁₀ can also be denoted as a five-bit integer.

8. Note the labeling of individual bits, such that X = x₄x₃x₂x₁x₀ and Y = y₄y₃y₂y₁y₀. The figure shows, in a pink color, the carries generated during the addition process. For example, a carry of 0 is generated when x₀ and y₀ are added; a carry of 1 is produced when x₁ and y₁ are added, and so on.

9. For bit position 0, there is no carry-in, and hence the addition is the same as for figure. a of Half adder . For each other bit position i, the addition involves bits x_i and y_i , and a carry-in c_i , as illustrated in above figure b. This observation leads to the design of a logic circuit that has three inputs x_i , y_i , and c_i , and produces the two outputs s_i and c _i+1.That we can achieve by using Full adder circuit.

NAND Logic:

 

 

NOR Logic:

 

Full Adder:

1. This circuit, which implements the addition of three bits, is called a full-adder.

2. Full adder having the 3 inputs and 2 outputs shown in block diagram

Fig. Full adder block diagram

3. Full adder truth table and outputs realization using K-map, logic circuit implementation is shown in below figure.       

Fig. Full adder.

4. For the carry-out function the optimal sum-of-products realization is

                        c _i+1 = x_i y_i + x_i c_i + y_i c_i

5. For the s_i function a sum-of-products realization is

              =   +     +    +       

  Implementing this function is by using the XOR gates, as explained below.

1. The XOR function of two variables is defined as x1 ⊕ x2 =  + . The preceding expression for the sum bit can be manipulated into a form that uses only XOR operations as follows

           = (  +  )   + (    +       

= (  ⊕ )  + (   ʘ )  

                                    = (  ⊕ )  + ( )   (⸫ x ʘ y =   )

                                                    = (xi ⊕ yi) ⊕ ci

2. The XOR operation is associative; hence we can write

=  ⊕  ⊕   

3. Therefore, a three-input XOR operation can be used to realize

Fig. A decomposed implementation of the full-adder circuit.

4. In view of the names used for the circuits, one can expect that a full-adder can be constructed using half-adders. This can be accomplished by creating a multilevel circuit given in above Figure. It uses two half-adders to form a full-adder.

AOI Logic:

 

NAND Logic:

NOR logic :

Subtractors:

1. The subtraction of two binary numbers may be accomplished by taking the complement of the subtrahend and adding it to the minuend.

2. By this, the subtraction operation becomes an addition operation and instead of having a separate circuit for subtraction, the adder itself can be used to perform subtraction. This results in reduction of hardware.

3. In subtraction, each subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form a difference bit.

4. If the minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the next significant position., that has been borrowed must be conveyed to the next  higher pair of bits by means of a signal coming out (output) of a given stage and going into (input) the next higher stage.

The Half-Subtractor:

1. A Half-subtractor is a combinational circuit that subtracts one bit from the other and produces the difference. It also has an output to specify if a 1 has been borrowed. . It is used to subtract the LSB of the subtrahend from the LSB of the minuend when one binary number is subtracted from the other.

2. A Half-subtractor is a combinational circuit with two inputs A and B and two outputs d and b. d indicates the difference and b is the output signal generated that informs the next stage that a 1 has been borrowed. When a bit B is subtracted from another bit A,  a difference bit (d) and a borrow bit (b) result according to the rules given as

3. The output borrow b is a 0 as long as A≥B. It is a 1 for A=0 and B=1. The d output is the result of the arithmetic operation 2b+A-B.

4. A circuit that produces the correct difference and borrow bits in response to every possible combination of the two 1-bit numbers is , therefore ,

                        d=  B+𝐴  = A⊕B and b=  B

5. That is, the difference bit is obtained by X-OR ing the two inputs, and the borrow bit is obtained by ANDing the complement of the minuend with the subtrahend.Note that logic for this exactly the same as the logic for output S in the half-adder.

6. A half-substractor can also be realized using universal logic either using only NAND gates or using NOR gates as:

NAND Logic:

NOR Logic:

The Full-Subtractor:

1. The half-subtractor can be only for LSB subtraction. If there is a  borrow during the subtraction of the LSBs, it affects the subtraction in the next higher column; the subtrahend bit is subtracted from the minuend bit, considering the borrow from that column used for the subtraction in the preceding column.

2. Such a subtraction is performed by a full-subtractor. It subtracts one bit (B) from another bit (A) , when already there is a borrow b_i from this column for the subtraction in the preceding column, and outputs the difference bit (d) and the borrow bit(b) required from the next d and b.

3. The two outputs present the difference and output borrow. The 1s and 0s for the output variables are determined from the subtraction of A-B-b_i.

4. From the truth table, a circuit that will produce the correct difference and borrow bits in response to every possiblecombinations of A,B and b_i is

5. A full-subtractor can be realized using X-OR gates and AOI gates as

6. The full subtractor can also be realized using universal logic either using only NAND gates or using NOR gates as:

NAND Logic:

NOR Logic:

Binary Parallel Adder:

1. A binary parallel adder is a digital circuit that adds two binary numbers in parallel form and produces the arithmetic sum of those numbers in parallel form. It consists of full adders connected in a chain , with the output carry from each full-adder connected to the input carry of the next full-adder in the chain.

1.The interconnection of four full-adder (FA) circuits to provide a 4-bit parallel adder. The augends bits of A and addend bits of B are designated by subscript numbers from right to left, with subscript 1 denoting the lower –order bit.

2. The carries are connected in a chain through the full-adders. The input carry to the adder is C_in and the output carry is C₄. The S output generates the required sum bits. When the 4-bit full-adder circuit is enclosed within an IC package, it has four terminals for the augends bits, four terminals for the addend bits, four terminals for the sum bits, and two terminals for the input and output carries.

3. An n-bit parallel adder requires n-full adders. It can be constructed from 4-bit, 2-bit and 1-bit full adder ICs by cascading several packages. The output carry from one package must be connected to the input carry of the one with the next higher –order bits. The 4-bit full adder is a typical example of an MSI function.

Ripple-Carry Adder:

1. To perform addition by hand, we start from the least-significant digit and add pairs of digits, progressing to the most-significant digit. If a carry is produced in position i, then this carry is added to the operands in position i + 1. The same arrangement can be used in a logic circuit that performs addition. For each bit position we can use a full-adder circuit, connected as shown in below figure

Fig. An n-bit ripple-carry adder.

2. Note that to be consistent with the customary way of writing numbers, the least-significant bit position is on the right. Carries that are produced by the full-adders propagate to the left.

3. When the operands X and Y are applied as inputs to the adder, it takes some time before the output sum, S, is valid. Each full-adder introduces a certain delay before its .   and .  outputs are valid. Let this delay be denoted as ∆t.   

4. Thus the carry-out from the first stage, , arrives at the second stage ∆t after the application of the  and  inputs. The carry-out from the second stage, , arrives at the third stage with a 2∆t delay, and so on.

5. The signal  is valid after a delay of (n − 1) ∆t, which means that the complete sum is available after a delay of n∆t.

6. Because of the way the carry signals “ripple” through the full-adder stages, the circuit in above figure is called a ripple-carry adder.

7. The delay incurred to produce the final sum and carry-out in a ripple-carry adder depends on the size of the numbers.

 4- Bit Parallel Subtractor:

1. The subtraction of binary numbers can be carried out most conveniently by means of complements , the subtraction A-B can be done by taking the 2‘s complement of B and adding it to A .

2. The 2‘s complement can be obtained by taking the 1‘s complement and adding 1 to the least significant pair of bits. The 1‘s complement can be implemented with inverters as

Binary-Adder Subtractor:

1. A 4-bit adder-subtractor, the addition and subtraction operations are combined into one circuit with one common binary adder. This is done by including an X-OR gate with each full-adder. The mode input M controls the operation. When M=0, the circuit is an adder, and when M=1, the circuit becomes a subtractor.

2. Each X-OR gate receives input M and one of the inputs of B. When M=0, B⊕0 = B .The full-adder receives the value B, input carry is 0 and the circuit performs A+B.  When M=1, B⊕1 =  and C1=1. The B inputs are complemented and a 1 is through the input carry. The circuit performs the operation A plus the 2‘s complement of B.

 

The Look-Ahead –Carry Adder:

1. In parallel-adder, the speed with which an addition can be performed is governed by the time required for the carries to propagate or ripple through all of the stages of the adder.

2. The look-ahead carry adder speeds up the process by eliminating this ripple carry delay. It examines all the input bits simultaneously and also generates the carry-in bits for all the stages simultaneously.

3. The method of speeding up the addition process is based on the two additional functions of the full-adder, called the carry generate and carry propagate functions.

4. Consider one full adder stage; say the nth stage of a parallel adder as shown in fig. we know that is made by two half adders and that the half adder contains an X-OR gate to produce the sum and an AND gate to produce the carry.

 5. If both the bits A_n and B_n are 1s, a carry has to be generated in this stage regardless of whether the input carry C_in is a 0 or a 1. This is called generated carry, expressed as G_n= A_n.B_n which has to appear at the output through the OR gate as shown in fig.

6. There is another possibility of producing a carry out. X-OR gate inside the half-adder  at the  input  produces an intermediary sum bit-  call it  P_n  –which is  expressed as P_{n =} A_n⊕B_{n .} Next P_n and C_n are added using the X-OR gate inside the second half adder to produce the final sum bit  and S_{n =} P_n⊕C_n   where  P_{n =} A_n⊕B_n  and  output  carry C₀= P_n.C_n =  (A_n⊕B_n )C_n which becomes carry for the (n+1)th stage.

7. Consider the case of both Pn and Cn being 1. The input carry Cn has to be propagated to the output only if Pn is 1. If Pn is 0, even if Cn is 1, the and gate in the second half-adder will inhibit Cn . the carry out of the nth stage is 1 when either Gn=1 or Pn.Cn =1 or both Gn and Pn.Cn are equal to 1. For the final sum and carry outputs of the nth stage, we get the following Boolean expressions.

8. Observe the recursive nature of the expression for the output carry at the nth stage which becomes the input carry for the (n+1)st stage .it is possible to express the output carry of a higher significant stage is the carry-out of the previous stage.

9. Based on these , the expression for the carry-outs of various full adders are as follows,

10. Observe that the final output carry is expressed as a function of the input variables in SOP form. Which is two level AND-OR or equivalent NAND-NAND form. Observe that the full look-ahead scheme requires the use of OR gate with (n+1) inputs and AND gates with number of inputs varying from 2 to (n+1).

2’s complement Addition and Subtraction using Parallel Adders:

1. Most modern computers use the 2‘s complement system to represent negative numbers and to perform subtraction operations of signed numbers can be performed using only the addition operation ,if we use the 2‘s complement form to represent negative numbers.

2. The circuit shown can perform both addition and subtraction in the 2‘s complement. This adder/subtractor circuit is controlled by the control signal ADD/SUB‘.

3. When the ADD/SUB‘level is HIGH, the circuit performs the addition of the numbers stored in registers A and B.  When the ADD/Sub‘level is LOW, the circuit subtract the number in register B from the number in register A. The operation is

When ADD/SUB‘is a 1:

1. AND gates 1,3,5 and 7 are enabled , allowing B0,B1,B2and B3 to pass to the OR gates 9,10,11,12 . AND gates 2,4,6 and 8 are disabled , blocking B0‘,B1‘,B2‘, and B3‘ from reaching the OR gates 9,10,11 and 12.

2. The two levels B0 to B3 pass through the OR gates to the 4-bit parallel adder, to be added to the bits A0 to A3. The sum appears at the output S0 to S3

3. Add/SUB‘=1 causes no carry into the adder.

When ADD/SUB‘is a 0:

1. AND gates 1,3,5 and 7 are disabled , allowing B0,B1,B2and B3 from reaching the OR gates 9,10,11,12 . AND gates 2,4,6 and 8 are enabled , blocking B0‘,B1‘,B2‘, and  B3‘ from reaching the OR gates.

 2.The two levels B0‘ to B3‘ pass through the OR gates to the 4-bit parallel adder, to be added to the bits A0 to A3.The C0 is now 1.thus the number in register B is converted to  its 2‘s complement form.

3. The difference appears at the output S0 to S3.

4. Adders/Subtractors used for adding and subtracting signed binary numbers. In computers , the output is transferred into the register A (accumulator) so that the result of the addition or subtraction always end up stored in the register A This is accomplished by applying a transfer pulse to the CLK inputs of register A.

 

Serial Adder:

1. A serial adder is used to add binary numbers in serial form. The two binary numbers to be added serially are stored in two shift registers A and B. Bits are added one pair at a time through a single full adder (FA) circuit as shown.

2. The carry out of the full-adder is transferred to a D flip- flop. The output of this flip-flop is then used as the carry input for the next pair of significant bits. The sum bit from the S output of the full-adder could be transferred to a third shift register.

3. By shifting the sum into A while the bits of A are shifted out, it is possible to use one register for storing both augend and the sum bits. The serial input register B can be used to transfer a new binary number while the addend bits are shifted out during the addition.

The operation of the serial adder is:

1. Initially register A holds the augend, register B holds the addend and the carry flip-flop is cleared to 0. The outputs (SO) of A and B provide a pair of significant bits for the full-adder at x and y.

2. The shift control enables both registers and carry flip-flop , so, at the clock pulse both registers are shifted once to the right, the sum bit from S enters the left most flip-flop of A , and the output carry is transferred into flip-flop Q .

3. The shift control enables the registers for a number of clock pulses equal to the number of bits of the registers. For each succeeding clock pulse a new sum bit is transferred to A, a new carry is transferred to Q, and both registers are shifted once to the right.

4. This process continues until the shift control is disabled. Thus the addition is accomplished by passing each pair of bits together with the previous carry through a single full adder circuit and transferring the sum, one bit at a time, into register A.

5. Initially, register A and the carry flip-flop are cleared to 0 and then the first number is added from B. While B is shifted through the full adder, a second number is transferred to it through its serial input.

6. The second number is then added to the content of register A while a third number is transferred serially into register B. This can be repeated to form the addition of two, three, or more numbers and accumulate their sum in register A.

Difference between Serial and Parallel Adders:

1. The parallel adder registers with parallel load, whereas the serial adder uses shift registers.

2. The number of full adder circuits in the parallel adder is equal to the number of bits in the binary numbers, whereas the serial adder requires only one full adder circuit and a carry flip- flop.

3. Excluding the registers, the parallel adder is a combinational circuit, whereas the serial adder is a sequential circuit. The sequential circuit in the serial adder consists of a full-adder and a flip-flop that stores the output carry.

BCD Adder:

The BCD addition process:

1. Add the 4-bit BCD code groups for each decimal digit position using ordinary binary addition.

2. For those positions where the sum is 9 or less, the sum is in proper BCD form and no correction is needed.

3. When the sum of two digits is greater than 9, a correction of 0110 should be added to that sum, to produce the proper BCD result. This will produce a carry to be added to the next decimal position.

A BCD adder circuit must be able to operate in accordance with the above steps.

In other words, the circuit must be able to do the following:

1. Add two 4-bit BCD code groups, using straight binary addition.

 2. Determine, if the sum of this addition is greater than 1101 (decimal 9); if it is , add 0110 (decimal 6) to this sum and generate a carry to the next decimal position.

1. The first requirement is easily met by using a 4- bit binary parallel adder such as the 74LS83 IC .For example , if the two BCD code groups A₃A₂A₁A₀and B₃B₂B₁B₀ are applied to a 4-bit parallel adder, the adder will output S₄S₃S₂S₁S₀ , where S4 is actually C₄ , the carry –out of the MSB bits.

2. The sum outputs S₄S₃S₂S₁S₀ can range anywhere from 00000 to 10010(when both the BCD code groups are 1001= 9). The circuitry for a BCD adder must include the logic needed to detect whenever the sum is greater than 01001, so that the correction can be added in. Those cases, where the sum is greater than 1001 are listed as:

3. Let us define a logic output X that will go HIGH only when the sum is greater than 01001 (i.e, for the cases in table). If examine these cases ,see that X will be HIGH for either of the following conditions:

a)      Whenever S₄ =1(sum greater than 15)

b)      Whenever S₃ =1 and either S₂ or S₁ or both are 1 (sum 10 to 15) This condition can be expressed as

            X=S₄+S₃(S₂+S₁)

4. Whenever X=1, it is necessary to add the correction factor 0110 to the sum bits, and to generate a carry. The circuit consists of three basic parts.

5. The two BCD code groups A₃A₂A₁A₀ and B₃B₂B₁B₀ are added together in the upper 4-bit adder, to produce the sum S₄S₃S₂S₁S_0. The logic gates shown implement the expression for X.

6. The lower 4-bit adder will add the correction 0110 to the sum bits, only when X=1, producing the final BCD sum output represented by

7. ∑₃∑₂∑₁∑_0. The X is also the carry-out that is produced when the sum is greater than 01001. When X=0, there is no carry and no addition of 0110. In such cases, ∑₃∑₂∑₁∑₀= S₃S₂S₁S_0.

8. Two or more BCD adders can be connected in cascade when two or more digit decimal numbers are to be added. The carry-out of the first BCD adder is connected as the carry-in of the second BCD adder, the carry-out of the second BCD adder is connected as the carry-in of the third BCD adder and so on.

 

EXCESS-3(XS-3) ADDER:

To perform Excess-3 additions,

1.        Add two xs-3 code groups

2.        If carry=1, add 0011(3) to the sum of those two code groups

If carry =0, subtract 0011(3) i.e., add 1101 (13 in decimal) to the sum of those two code groups.

Ex: Add 9 and 5         

                                    1100    9 in Xs-3

                                  +1000    5 in xs-3

                                    ___ _ _ __

                        1          0100    there is a carry

                +0011          0011    add 3 to each group

              ----------          ----------

                 0100           0111       14 in xs-3

                  (1)             (4)

EX:

1. Implementation of xs-3 adder using 4-bit binary adders is shown. The augend (A3 A2A1A0) and addend (B3B2B1B0) in xs-3 are added using the 4-bit parallel adder. If the carry is a 1, then 0011(3) is added to the sum bits S3S2S1S0 of the upper adder in the lower 4-bit parallel adder.

2. If the carry is a 0, then 1101(3) is added to the sum bits (This is equivalent to subtracting 0011(3) from the sum bits. The correct sum in xs-3 is obtained.

Excess-3 (XS-3) Subtractor:

To perform Excess-3 subtraction,

1.                 Complement the subtrahend

2.                 Add the complemented subtrahend to the minuend.

3.                 If carry =1, result is positive. Add 3 and end around carry to the result . If carry=0, the result is negative. Subtract 3, i.e, and take the 1‘s complement of the result.

Ex:    Perform 9-4

                        1100    9 in xs-3

                       +1000   Complement of 4 n Xs-3

                        --------

            (1)        0100    There is a carry

 

                        +0011  Add 0011(3)

                     ------------

                          0111

                                1  End around carry

                      ------------

                          1000  5 in xs-3

1. The minuend and the 1‘s complement of the subtrahend in xs-3 are added in the upper 4- bit parallel adder.

2. If the carry-out from the upper adder is a 0, then 1101 is added to the sum bits of the upper adder in the lower adder and the sum bits of the lower adder are complemented to get the result. If the carry-out from the upper adder is a 1, then 3=0011 is added to the sum bits of the lower adder and the sum bits of the lower adder give the result.

2.3.2. Multiplexers (Data Selector):

1. A multiplexer circuit has a number of data inputs, one or more select inputs, and one output. It passes the signal value on one of the data inputs to the output. The data input is selected by the values of the select inputs.

Fig. Multiplexer block diagram

2. Below figure shows a 2-to-1 multiplexer. Part (a) gives the symbol commonly used. The select input, s, chooses as the output of the multiplexer either input w0 or w1. The multiplexer’s functionality can be described in the form of a truth table as shown in part (b) of the figure. Part (c) gives a sum-of-products implementation of the 2-to-1 multiplexer.

Fig. A 2-to-1 multiplexer.

3. Below figure a depicts a larger multiplexer with four data inputs, w0, . . . ,w3, and two select inputs, s1 and s0. As shown in the truth table in part (b) of the figure, the two-bit number represented by s1s0 selects one of the data inputs as the output of the multiplexer

Fig. A 4-to-1 multiplexer.

4. A sum-of-products implementation of the 4-to-1 multiplexer appears in Figure 4.2c. It

     realizes the multiplexer function

            f = s₁s₀w₀ + s₁s₀w₁ + s₁s₀w₂ + s₁s₀w₃

5. It is possible to build larger multiplexers using the same approach. Usually, the number of data inputs, n, is an integer power of two.

6. A multiplexer that has n data inputs, w0, . . . ,wn−1, requires [log2n] select inputs. Larger multiplexers can also be constructed from smaller multiplexers.

For example, the 4-to-1 multiplexer can be built using three 2-to-1 multiplexers as illustrated in below figure.

Fig. Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.

Below figure  shows how a 16-to-1 multiplexer is constructed with five 4-to-1 multiplexers.

Fig. A 16-to-1 multiplexer.

Synthesis of Logic Functions Using Multiplexers:

1. Multiplexers are useful in many practical applications. They can also be used in a more general way to synthesize logic functions. Consider the example in below figure a.

2. The truth table defines the function f = w₁ ⊕ w₂. This function can be implemented by a 4-to-1 multiplexer in which the values of f in each row of the truth table are connected as constants to the multiplexer data inputs.

3. The multiplexer select inputs are driven by w₁ and w₂. Thus for each valuation of w₁w₂, the output f is equal to the function value in the corresponding row of the truth table

Fig . Synthesis of a logic function using multiplexers.

4. The above implementation is straightforward, but it is not very efficient. A better implementation can be derived by manipulating the truth table as indicated in above figure b, which allows f to be implemented by a single 2-to-1 multiplexer.

5. One of the input signals, w1 in this example, is chosen as the select input of the 2-to-1 multiplexer. The truth table is redrawn to indicate the value of f for each value of w1.

6. When w1 = 0, f has the same value as input w2, and when w1 = 1, f has the value of w2. The circuit that implements this truth table is given in above figure c. This procedure can be applied to synthesize a circuit that implements any logic function.

7. Below figure a gives the truth table for the three-input majority function, and it shows how the truth table can be modified to implement the function using a 4-to-1 multiplexer. Any two of the three inputs may be chosen as the multiplexer select inputs. We have chosen w₁ and w₂ for this purpose, resulting in the circuit in Figure b.

Fig. Implementation of the three-input majority function

using a 4-to-1 multiplexer.

2.3.3. Decoders:

2 to 4 Decoder:

1. Consider the logic circuit in below figure. It has two inputs, w₁ and w₀, and four outputs, y₀, y₁, y₂, and y₃. As shown in the truth table, only one of the outputs is asserted at a time, and each output corresponds to one valuation of the inputs. Setting the inputs w₁w₀ to 00, 01, 10, or 11 causes the output y₀, y₁, y₂, or y₃ to be set to 1, respectively.

2. This type of circuit is called a binary decoder. Its inputs represent a binary number, which is decoded to assert the corresponding output. A circuit symbol and logic circuit for this decoder are shown in parts (b) and (c) of the figure. Each output is driven by an AND gate that decodes the corresponding valuation of w₁w₀.

Fig. 2 to 4 decoder truth table and block diagram

Fig. A 2-to-4 decoder Logic circuit

3. It is useful to include an enable input, En, in a decoder circuit, as illustrated in below figure. When enabled by setting En = 1 the decoder behaves as presented in above figure.

Fig. 2 to 4 decoder with enable input

4. But, if it is disabled by setting E_n = 0, then none of the outputs are asserted. Note that only five rows are shown in the truth table, because if E_n = 0 then all outputs are equal to 0 regardless of the values of w1 and w0.

5. The truth table indicates this by showing x when it does not matter whether the variable in question has the value 0 or 1.

6.  A graphical symbol for this decoder is given in Figure b. Part (c) of the figure shows how the enable capability can be included in the decoder of Figure c.

7. A binary decoder with n inputs has 2n outputs. A graphical symbol for an n-to-2n decoder is shown in Figure d.

Fig. Binary decoder.

Fig. A 3-to-8 decoder using two 2-to-4 decoders.

3-to-8 decoder:

         Number of inputs = 3, Number of outputs = 8

Fig. Binary to octal decoder(3-to-8 decoder)

Fig. Truth table

 

Fig. Logic circuit

2.3.4.Demultiplexers:

1. A multiplexer has one output, n data inputs, and [log₂n] select inputs. The purpose of the multiplexer circuit is to multiplex the n data inputs onto the single data output under control of the select inputs.

2. A circuit that performs the opposite function, namely, placing the value of a single data input onto multiple data outputs, is called a demultiplexer.

Fig. De multiplexer block diagram

1- to- 4 Demultiplexer:

No. of Inputs = 1, No.of.outputs= 4, No. of select inputs = 2

Fig.Truth table and block diagram

Fig. Logic circuit

2.3.5. Encoders:

1. An encoder performs the opposite function of a decoder. It encodes given information into a more compact form.

2. A binary encoder encodes information from 2ⁿ inputs into an n-bit code, as indicated in Figure. Exactly one of the input signals should have a value of 1, and the outputs present the binary number that identifies which input is equal to 1.

Fig. A 2ⁿ-to-n binary encoder.

4-to-2 encoder:

No. of inputs = 4, No.of outputs = 2

From truth table observe that the output y₀ is 1 when either input w₁ or w₃ is 1, and output y1 is 1 when input w₂ or w₃ is 1. Hence these outputs can be generated by the circuit in Figure b.

8-to-3 encoder:

Fig. Truth table and block diagram

Fig. Logic diagram

Decimal to BCD encoder:

Fig. Truth table and block diagram

Fig. Logic diagram

Parity Encoders:

1. Another useful class of encoders is based on the priority of input signals. In a priority encoder each input has a priority level associated with it. The encoder outputs indicate the active input that has the highest priority.

2. When an input with a high priority is asserted, the other inputs with lower priority are ignored. The truth table for a 4-to-2 priority encoder is shown in Figure.

Fig .Truth table for a 4-to-2 priority encoder.

3. It assumes that w₀ has the lowest priority and w₃ the highest. The outputs y₁ and y₀ represent the binary number that identifies the highest priority input set to 1. Since it is possible that none of the inputs is equal to 1, an output, z, is provided to indicate this condition.

4. It is set to 1 when at least one of the inputs is equal to 1. It is set to 0 when all inputs are equal to 0. The outputs y₁ and y₀ are not meaningful in this case, and hence the first row of the truth table can be treated as a don’t-care condition for y₁ and y₀.

5. The behavior of the priority encoder is most easily understood by first considering the last row in the truth table. It specifies that if input w₃ is 1, then the outputs are set to y₁y₀ = 11.

6. Because w₃ has the highest priority level, the values of inputs w₂, w₁, and w₀ do not matter. To reflect the fact that their values are irrelevant, w₂, w₁, and w₀ are denoted by the symbol x in the truth table.

7. The second-last row in the truth table stipulates that if w₂ = 1, then the outputs are set to y₁y₀ = 10, but only if w₃ = 0. Similarly, input w₁ causes the outputs to be set to y₁y₀ = 01 only if both w₃ and w₂ are 0. Input w₀ produces the outputs y₁y₀ = 00 only if w₀ is the only input that is asserted.

2.3.6. Code converters:

1. The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another.

2. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus a code converter is a logic circuit whose inputs are bit patterns representing numbers (or character) in one cod and whose outputs are the corresponding representation in a different code. Code converters are usually multiple output circuits.

3. To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational circuit performs this transformation by means of logic gates.

4. For example, a binary –to-gray code converter has four binary input lines B₄, B_3,B₂,B₁ and four gray code output lines G_4,G_3,G_2,G₁. When the input is 0010, for instance, the output should be 0011 and so forth. To design a code converter, we use a code table treating it as a truth table to express each output as a Boolean algebraic function of all the inputs.

5. In this example, of binary –to-gray code conversion, we can treat the binary to the gray code table as four truth tables to derive expressions for G_4, G3, G2, and G1. Each of these four expressions would, in general, contain all the four input variables B₄, B3,B₂,and B1_. Thus, this code converter is actually equivalent to four logic circuits, one for each of the truth tables.

6. The logic expression derived for the code converter can be simplified using the usual techniques, including ‗don‘t cares‘ if present. Even if the input is an un weighted code, the same cell numbering method which we used earlier can be used, but the cell numbers --must correspond to the input combinations as if they were an 8-4-2-1 weighted code. s

Design of a 4-bit binary to gray code converter:

Design of a 4-bit gray to Binary code converter:

Design of a 4-bit BCD to XS-3 code converter:

Design of a BCD to gray code converter:

 

 

 

2.3.7. Comparators:

1- bit  Magnitude Comparator:

2- bit Magnitude Comparator:

 

 

4- Bit Magnitude Comparator:

 

 

IC comparator:

 

 

2.3.8. Parity generator and Parity Checker:

1. The parity generator and parity checker’s main function is to detect errors in data transmission .The parity bit is an extra bit that is set at the transmission side to either ‘0’ or ‘1’, it is used to detect only single bit error and it is the easiest method for detecting errors.

2. There are different types of error detection codes used to detect the errors they are parity, ring counter, block parity code, Hamming code etc. The brief explanation about parity bit, parity generator and checker are explained below.

3. What is Parity Bit?

    Definition: The parity bit or check bit are the bits added to the binary code to check whether the particular code is in parity or not, for example, whether the code is in even parity or odd parity is checked by this check bit or parity bit. The parity is nothing but number of 1’s and there are two types of parity bits they are even bit and odd bit.

4. In odd parity bit, the code must be in an odd number of 1’s, for example, we are taking 5-bit code 100011, this code is said to be odd parity because there is three number of 1’s in the code which we have taken. In even parity bit the code must be in even number of 1’s, for example, we are taking 6-bit code 101101, this code is said to be even parity because there are four number of 1’s in the code which we have taken

5. What is the Parity Generator?

    Definition: The parity generator is a combination circuit at the transmitter, it takes an original message as input and generates the parity bit for that message and the transmitter in this generator transmits messages along with its parity bit.

6. Types of Parity Generator

   The classification of this generator is shown in the below figure

Even Parity Generator:

1. The even parity generator maintains the binary data in even number of 1’s, for example, the data taken is in odd number of 1’s, this even parity generator is going to maintain the data as even number of 1’s by adding the extra 1 to the odd number of 1’s.

2. This is also a combinational circuit whose output is dependent upon the given input data, which means the input data is binary data or binary code given for parity generator.

3. Let us consider three input binary data, that three bits are considered as A, B, and C. We can write 8 combinations using the three input binary data that is from 000 to 111 (0 to 7), total eight combinations will get from the given three input binary data which we have considered. The truth table of even parity generator for three input binary data is shown below.

     0 0 0 – In this input binary code the even parity is taken as ‘0’ because the input is already in even parity, so no need to add even parity once again for this input.

     0 0 1 – – In this input binary code there is only a single number of ‘1’ and that single number of ‘1’ is an odd number of ‘1’. If an odd number of ‘1’ is there, then even parity generator must generate another ‘1’ to make it as even parity, so even parity is taken as 1 to make the 0 0 1 code into even parity.

     0 1 0 –  This bit is in odd parity so even parity is taken as 1 to make the 0 1 0 code into even parity.

     0 1 1 – This bit is already in even parity so even parity is taken as 0 to make the 0 1 1 code into even parity.

      1 0 0 – This bit is in odd parity so even parity is taken as 1 to make the 1 0 0 code into even parity.

      1 0 1 – This bit is already in even parity so even parity is taken as 0 to make the 1 0 1 code into even parity.

      1 1 0 – This bit is also in even parity so even parity is taken as 0 to make the 1 1 0 code into even parity.

      1 1 1 – This bit is in odd parity so even parity is taken as 1 to make the 1 1 1 code into even parity.                         Even Parity Generator Truth Table

A B C	Even Parity
0  0 0	0
0  0 1	1
0  1 0	1
0  1 1	0
1  0 0	1
1  0 1	0
1  1 0	0
1  1 1	1

 

4. The karnaugh map (k-map) simplification for three-bit input even parity is

k-map-for-even-parity-generator

5. From the above even parity truth table, the parity bit simplified expression is written as

6. The even parity expression implemented by using two Ex-OR gates and the logic diagram of  this even parity using the Ex-OR logic gate is shown below.

Even-parity-logic-circuit

7. In this way, the even parity generator generates an even number of 1’s by taking the input data

Odd Parity Generator

1. The odd parity generator maintains the binary data in an odd number of 1’s, for example, the data taken is in even number of 1’s, this odd parity generator is going to maintain the data as an odd number of 1’s by adding the extra 1 to the even number of 1’s.

2. This is the combinational circuit whose output is always dependent upon the given input data.  If there is an even number of 1’s then only parity bit is added to make the binary code into an odd number of 1’s.

3. Let us consider three input binary data, that three bits are considered as A, B, and C. The truth table of odd parity generator for three input binary data is shown below.

     0 0 0 – In this input binary code the odd parity is taken as ‘1’ because the input is in even parity.

     0 0 1 –  This binary input is already in odd parity, so odd parity is taken as 0.

     0 1 0 – This binary input is also in odd parity, so odd parity is taken as 0.

     0 1 1 – This bit is in even parity so odd parity is taken as 1 to make the 0 1 1 code into odd parity.

     1 0 0 – This bit is already in odd parity, so odd parity is taken as 0 to make the 1 0 0 code into odd parity.

     1 0 1 – This input bit is in even parity, so odd parity is taken as 1 to make the 1 0 1 code into odd parity.

     1 1 0 – This bit is in even parity, so odd parity is taken as 1.

     1 1 1 – This input bit is in odd parity, so odd parity is taken as 0.

Odd Parity Generator Truth Table

 

A B C	Odd Parity
0  0 0	1
0  0 1	0
0  1 0	0
0  1 1	1
1  0 0	0
1  0 1	1
1  1 0	1
1  1 1	0

 

k-map-for-odd-parity-generator

From the above odd parity truth table, the parity bit simplified expression is written as

The logic diagram of this odd parity generator is shown below.

Logic-circuit

In this way, the odd parity generator generates an odd number of 1’s by taking the input data

 What is the Parity Check?

  Definition: The combinational circuit at the receiver is the parity checker. This checker takes the received message including the parity bit as input. It gives output ‘1’ if there is some error found and gives output ‘0’ if no error is found in the message including the parity bit.

Types of Parity Checker

The classification of the parity checker is shown in the below figure

Even Parity Checker:

1. In even parity checker if the error bit (E) is equal to ‘1’, then we have an error. If error bit E=0 then indicates there is no error.

            Error Bit (E) =1, error occurs

            Error Bit (E) =0, no error

2. The parity checker circuit is shown in the below figure

Logic circuit

Odd Parity Checker:

1. In odd parity checker if an error bit (E) is equal to ‘1’, then it indicates there is no error. If an error bit E=0 then indicates there is an error.

            Error Bit (E) =1, no error

            Error Bit (E) =0, error occurs

2. The parity checker won’t be able to detect if there are errors in more than ‘1’ bit and the correct of data is also not possible, these are the main disadvantages of the parity checker.

3. Advantages of Parity

a)      Simplicity

b)      Easy to use

4. Applications of Parity

a)      In digital systems and many hardware applications, this parity is used

b)      The parity bit is also used in Small Computer System Interface (SCSI) and also in Peripheral Component Interconnect (PCI) to detect the errors

         1). What is the difference between the parity generator and parity checker?

         The parity generator generates the parity bit in the transmitter and the parity checker checks the parity bit in the receiver.

         2). What does no parity mean?

         When the parity bits are not used to check for errors then the parity bit is said to be non-parity or no parity or the absence of parity.

         3). What is the parity value?     

         The parity value concept used for both commodities and securities and the term refers to when the value of the two assets is equal.

         4). Why do we need a parity checker?

         The parity checker is needed to detect the errors in communication and also in the memory storage devices parity checker is used for testing.         

         5). How can the parity bit detect a damaged data unit?

         The redundant bit in this technique is called a parity bit, it detects damaged data unit when an error occurs during the transmission of data.

2.3.9. BCD to 7 segment converter (decoder):

 

Introduction:

 

1. A digital or binary decoder is a digital combinational logic circuit which can convert one form of digital code into another form.

 

2. BCD to 7-segment display decoder is a special decoder which can convert binary coded decimals into another form which can be easily displayed through a 7-segment display.

 

3. BCD:

     BCD stands for binary coded decimal. It is a digital numbering system in which we can represent each decimal number using 4 bits of binary numbers.

 

4. There are 10 digits in the decimal system. To represent all 10 digits we need 10 combinations of 4 binary bits.

 

5. A digital system like a computer can understand and easily read a large number in binary format. However, a human cannot read large binary numbers. To solve this problem we need to display it as a decimal digit using 7-segment display.

 

6. 7-Segment Display :

     It is a digital device that can be used for displaying decimal number, alphabets, and characters.

7. 7-Segment display contains 7 LED segments arranged in a shape given in figure above. Generally, there are 8 input pins in a 7-Segment display. 7 input pins for each of the 7 LEDs and one pin for the common terminal.

 

8. Here are two types of 7-Segment displays.

 

a)      Common Cathode

In such type of 7-segment display, all the cathodes of the 7 LEDs are connected together to form a common terminal. It should be connected to GND or logic ‘0’ during its operation.

 

To illuminate any LED of the display, you need to supply logic ‘1’ to its corresponding input pin.

 

b)      Common Anode

The type of 7-Segment display in which all the anode terminals of 7 LEDs are connected together to form common anode terminal. This terminal should be connected with Vcc or logic ‘1’ during its operation.

 

            To illuminate any of the LED segments we need to provide logic ‘0’ to it.

 

Working of 7-Segment Display (LED) Circuit :

 

1. 7 LED segments of the display and their pins are “a”, “b”, “c”, “d”, “e”, “f” & “g” as shown in the figure given below. Each of the pins will illuminate the specific segment only.

 

2. We assume common cathode LED segment as our example.

 

3. Suppose we want to display digit ‘0’, in order to display 0, we need to turn on “a”, “b”, “c”, “d”, “e”, “f”. & turn-off the “g”.

 

4. 7-Segment Display Segments for all Numbers Display combination of decimal numbers is given below.

 

Fig. Truth table 7-segment decoder

5.  Karnaugh Maps Simplification

     For other combinations of input, the output is “don’t care X” as there are no more digits to display. We will derive the expression for each output using Karnaugh map (K-MAP).

     For output a:

For output b:

For output c:

 

For output d:

 

 

For output e:

 

 

For output f:

 

For output g:

 

7-Segment Display Decoder Circuit :

     We have derived an expression for each output now we need to make its schematic using logic gates as shown in the figure given below. Fig: Schematic of BCD to 7-Segment Display Decoder.